The present invention is directed to a clock signal generator for an integrated circuit and, more particularly, to a gated clock signal generator for use with dual-edge triggered circuits.
Conventional clocked circuits, such as flip flops or edge triggered gates, are triggered by a single edge of the clock signal. The triggering edge of the clock signal may be either the positive or negative edge, more generally the asserting or de-asserting edge. However, clocked circuits can alternatively be triggered by both clock signal edges (asserting and de-asserting). The clocking rate for dual-edge triggered circuits is nearly double the clocking rate for a conventional single-edge triggered circuit clocked by the same clock signal.
Power consumed by the clock trees, which is a function of clock frequency, is a substantial proportion of the total power of certain integrated circuits (ICs), even as high as 40% in some cases. The power consumed by the clock trees can be maintained for faster clocking rates of the dual-edge clocked circuits, or can be reduced for similar clocking rates when the clocked circuits are triggered by both edges. Savings can also be achieved in the clocked circuits themselves compared to equivalent single edge triggered modules.
An issue arises with gating the clock signals for dual-edge triggered circuits. If a conventional gated single-edge clock signal generator is used with dual-edge triggered circuits, functional limitations appear. For example, a transition of the gate signal risks resulting in loss of clock signal edges, or in additional, unwanted clock signal edges. Efforts made to avoid these risks may lead to undue complication of the dual-edge clock signal generator with consequent additional cost and operational difficulties.